<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
  <head>
    <title>ID_ISAR4</title>
    <link href="insn.css" rel="stylesheet" type="text/css"/>
  </head>
  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ID_ISAR4, Instruction Set Attribute Register 4</h1><p>The ID_ISAR4 characteristics are:</p><h2>Purpose</h2>
        <p>Provides information about the instruction sets implemented by the PE in AArch32 state.</p>

      
        <p>Must be interpreted with <a href="AArch32-id_isar0.html">ID_ISAR0</a>, <a href="AArch32-id_isar1.html">ID_ISAR1</a>, <a href="AArch32-id_isar2.html">ID_ISAR2</a>, <a href="AArch32-id_isar3.html">ID_ISAR3</a>, and <a href="AArch32-id_isar5.html">ID_ISAR5</a>.</p>

      
        <p>For general information about the interpretation of the ID registers, see <span class="xref">'Principles of the ID scheme for fields in ID registers'</span>.</p>
      <h2>Configuration</h2><p>AArch32 System register ID_ISAR4 bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-id_isar4_el1.html">ID_ISAR4_EL1[31:0]</a>.</p><p>This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ID_ISAR4 are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>ID_ISAR4 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-31_28">SWP_frac</a></td><td class="lr" colspan="4"><a href="#fieldset_0-27_24">PSR_M</a></td><td class="lr" colspan="4"><a href="#fieldset_0-23_20">SynchPrim_frac</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">Barrier</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">SMC</a></td><td class="lr" colspan="4"><a href="#fieldset_0-11_8">Writeback</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">WithShifts</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">Unpriv</a></td></tr></tbody></table><h4 id="fieldset_0-31_28">SWP_frac, bits [31:28]</h4><div class="field">
      <p>Indicates support for the memory system locking the bus for SWP or SWPB instructions. Defined values are:</p>
    <table class="valuetable"><tr><th>SWP_frac</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>SWP or SWPB instructions not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>SWP or SWPB implemented but only in a uniprocessor context. SWP and SWPB do not guarantee whether memory accesses from other Requesters can come between the load memory access and the store memory access of the SWP or SWPB.</p>
        </td></tr></table><p>All other values are reserved. This field is valid only if <a href="AArch32-id_isar0.html">ID_ISAR0</a>.Swap is <span class="binarynumber">0b0000</span>.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0000</span>.</p></div><h4 id="fieldset_0-27_24">PSR_M, bits [27:24]</h4><div class="field">
      <p>Indicates the implemented M-profile instructions to modify the PSRs. Defined values are:</p>
    <table class="valuetable"><tr><th>PSR_M</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>None implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Adds the M-profile forms of the CPS, MRS, and MSR instructions.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0000</span>.</p></div><h4 id="fieldset_0-23_20">SynchPrim_frac, bits [23:20]</h4><div class="field">
      <p>Used in conjunction with <a href="AArch32-id_isar3.html">ID_ISAR3</a>.SynchPrim to indicate the implemented Synchronization Primitive instructions. Possible values are:</p>
    <table class="valuetable"><tr><th>SynchPrim_frac</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>If SynchPrim == <span class="binarynumber">0b0000</span>, no Synchronization Primitives implemented. If SynchPrim == <span class="binarynumber">0b0001</span>, adds the LDREX and STREX instructions. If SynchPrim == <span class="binarynumber">0b0010</span>, also adds the CLREX, LDREXB, LDREXH, STREXB, STREXH, LDREXD, and STREXD instructions.</p>
        </td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>If SynchPrim == <span class="binarynumber">0b0001</span>, adds the LDREX, STREX, CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions.</p>
        </td></tr></table><p>All other combinations of SynchPrim and SynchPrim_frac are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0000</span>.</p></div><h4 id="fieldset_0-19_16">Barrier, bits [19:16]</h4><div class="field">
      <p>Indicates the implemented Barrier instructions in the A32 and T32 instruction sets. Defined values are:</p>
    <table class="valuetable"><tr><th>Barrier</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>None implemented. Barrier operations are provided only as System instructions in the (coproc==<span class="binarynumber">0b1111</span>) encoding space.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Adds the DMB, DSB, and ISB barrier instructions.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-15_12">SMC, bits [15:12]</h4><div class="field">
      <p>Indicates the implemented SMC instructions. Defined values are:</p>
    <table class="valuetable"><tr><th>SMC</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>None implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Adds the SMC instruction.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the permitted values are:</p>
<ul>
<li>
<p>If EL3 is implemented, the only permitted value is <span class="binarynumber">0b0001</span>.</p>

</li><li>
<p>If neither EL3 nor EL2 is implemented, the only permitted value is <span class="binarynumber">0b0000</span>.</p>

</li></ul></div><h4 id="fieldset_0-11_8">Writeback, bits [11:8]</h4><div class="field">
      <p>Indicates the support for Writeback addressing modes. Defined values are:</p>
    <table class="valuetable"><tr><th>Writeback</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Basic support. Only the LDM, STM, PUSH, POP, SRS, and RFE instructions support writeback addressing modes. These instructions support all of their writeback addressing modes.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Adds support for all of the writeback addressing modes.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-7_4">WithShifts, bits [7:4]</h4><div class="field">
      <p>Indicates the support for instructions with shifts. Defined values are:</p>
    <table class="valuetable"><tr><th>WithShifts</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Nonzero shifts supported only in MOV and shift instructions.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Adds support for shifts of loads and stores over the range LSL 0-3.</p>
        </td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>As for <span class="binarynumber">0b0001</span>, and adds support for other constant shift options, both on load/store and other instructions.</p>
        </td></tr><tr><td class="bitfield">0b0100</td><td>
          <p>As for <span class="binarynumber">0b0011</span>, and adds support for register-controlled shift options.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0100</span>.</p></div><h4 id="fieldset_0-3_0">Unpriv, bits [3:0]</h4><div class="field">
      <p>Indicates the implemented unprivileged instructions. Defined values are:</p>
    <table class="valuetable"><tr><th>Unpriv</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>None implemented. No T variant instructions are implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Adds the LDRBT, LDRT, STRBT, and STRT instructions.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>As for <span class="binarynumber">0b0001</span>, and adds the LDRHT, LDRSBT, LDRSHT, and STRHT instructions.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0010</span>.</p></div><div class="access_mechanisms"><h2>Accessing ID_ISAR4</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b0000</td><td>0b0010</td><td>0b100</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T0 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T0 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TID3 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TID3 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        R[t] = ID_ISAR4;
elsif PSTATE.EL == EL2 then
    R[t] = ID_ISAR4;
elsif PSTATE.EL == EL3 then
    R[t] = ID_ISAR4;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
</html>
